View CY62256VNLL-70ZRXI_5067486.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY62256VN
256K (32K x 8) Static RAM
256K (32K x 8) Static RAM
Features
Functional Description
The CY62256VN[1] family is composed of two high performance CMOS static RAM's organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tristate drivers. These devices have an automatic power down feature, reducing the power consumption by over 99% when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.
Temperature ranges Commercial: 0 C to +70 C Industrial: -40 C to +85 C Automotive-A: -40 C to +85 C Automotive-E: -40 C to +125 C Speed: 70 ns Low voltage range: 2.7 V to 3.6 V Low active power and standby power Easy memory expansion with CE and OE features TTL compatible inputs and outputs Automatic power down when deselected CMOS for optimum speed and power Available in standard Pb-free and non Pb-free 28-pin (300-mil) narrow SOIC, 28-pin TSOP-I, and 28-pin reverse TSOP-I packages

Logic Block Diagram
INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE A14 A13 A12 A11 A1 A0 ROW DECODER
I/O0 I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5
32K x 8 ARRA Y
COLUMN DECODER
POWER DOWN
I/O6 I/O7
.
Note 1. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document Number: 001-06512 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 4, 2011
[+] Feedback
CY62256VN
Contents
Product Portfolio .............................................................. 3 Pin Configurations ........................................................... 3 Pin Definitions .................................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Typical DC and AC Characteristics ................................ 9 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14
Document Number: 001-06512 Rev. *D
Page 2 of 14
[+] Feedback
CY62256VN
Product Portfolio
Product CY62256VNLL CY62256VNLL CY62256VNLL CY62256VNLL Range Min Commercial Industrial Automotive-A Automotive-E 2.7 2.7 2.7 2.7 VCC Range (V) Typ[2] 3.0 3.0 3.0 3.0 Max 3.6 3.6 3.6 3.6 Power Dissipation Operating, ICC (mA) Typ[2] 11 11 11 11 Max 30 30 30 30 Standby, ISB2 (A) Typ[2] 0.1 0.1 0.1 0.1 Max 5 10 10 130
Pin Configurations
Narrow SOIC Top View
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3
OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11
22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8
TSOP I Top View (not to scale)
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12
A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE
7 6 5 4 3 2 1 28 27 26 25 24 23 22
8 9 10 11 12 13 14 15 16 17 18 19 20 21
TSOP I Reverse Pinout Top View (not to scale)
A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0
Pin Definitions
Pin Number 1-10, 21, 23-26 Input 11-13, 15-19 27 20 22 14 28 Input/Output Input/Control Input/Control Input/Control Ground Power Supply Type A0-A14. Address inputs I/O0-I/O7. Data lines. Used as input or output lines depending on operation. WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted. CE. When LOW, selects the chip. When HIGH, deselects the chip OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins GND. Ground for the device VCC. Power supply for the device Description
Note 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25 C, and tAA = 70 ns.
Document Number: 001-06512 Rev. *D
Page 3 of 14
[+] Feedback
CY62256VN
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ -65 C to +150 C Ambient temperature with power applied ........................................... -55 C to +125 C Supply voltage to ground potential (pin 28 to pin 14)...........................................-0.5 V to +4.6 V DC voltage applied to outputs in high Z State[3] .................................. -0.5 V to VCC + 0.5 V DC input voltage[3] ............................... -0.5 V to VCC + 0.5 V Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, method 3015) Latch-up current .................................................... > 200 mA
Operating Range
Device Range Ambient Temperature (TA)[4] 0 C to +70 C -40 C to +85 C -40 C to +85 C VCC 2.7 V to 3.6 V
CY62256VN Commercial Industrial Automotive-A
Automotive-E -40 C to +125 C
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current GND < VIN < VCC Commercial/ Indusrial/ Automotive-A Automotive-E IOZ Output leakage current GND < VIN < VCC, Output Disabled Commercial/ Indusrial/ Automotive-A Automotive-E ICC ISB1 ISB2 VCC operating supply current VCC = 3.6 V, IOUT = 0 mA, f = fMAX = 1/tRC All ranges IOH = 1.0 mA IOL = 2.1 mA Test Conditions VCC = 2.7 V VCC = 2.7 V -70 Min 2.4 - 2.2 -0.5 -1 Typ[5] - - - - - Max - 0.4 VCC + 0.3V 0.8 +1 Unit V V V V A
-10 -1
- -
+10 +1
A A
-10 - - - - -
- 11 100 0.1
+10 30 300 5 10 130
A mA A A
Automatic CE power VCC = 3.6 V, CE > VIH, All ranges down current - TTL inputs VIN > VIH or VIN < VIL, f = fMAX Automatic CE power down current - CMOS inputs VCC = 3.6 V, CE > VCC - 0.3 V, Commercial VIN > VCC - 0.3 V or VIN < 0.3 V, Indusrial/ f=0 Automotive-A Automotive-E
Notes 3. VIL (min) = -2.0 V for pulse durations of less than 20 ns. 4. TA is the "Instant-On" case temperature. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25 C, and tAA = 70 ns.
Document Number: 001-06512 Rev. *D
Page 4 of 14
[+] Feedback
CY62256VN
Capacitance
Parameter[6] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.0 V Max 6 8 Unit pF pF
Thermal Resistance
Parameter[6] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Figure 1. AC Test Loads and Waveforms
R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC 10% GND < 5 ns Equivalent to: THEVENIN EQUIVALENT Rth OUTPUT Vth ALL INPUT PULSES 90% 90% 10% < 5 ns
Test Conditions Still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board
SOIC 68.45 26.94
TSOPI 87.62 23.73
RTSOPI 87.62 23.73
Unit C/W C/W
Parameter R1 R2 RTH VTH
Value 1100 1500 645 1.750
Units Ohms Ohms Ohms Volts
Data Retention Characteristics
(Over the Operating Range) Parameter VDR ICCDR Description VCC for data retention Data retention current VCC = 1.4 V, CE > VCC - 0.3 V, VIN > VCC - 0.3 V or VIN < 0.3 V Commercial Indusrial/ Automotive-A Automotive-E Conditions[7] Min 1.4 - - - 0 tRC - - Typ[8] - 0.1 Max - 3 6 50 - - ns ns Unit V A
tCDR[6] tR[6]
Chip deselect to data retention time Operation recovery time
Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. No input may exceed VCC + 0.3 V. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25 C, and tAA = 70 ns.
Document Number: 001-06512 Rev. *D
Page 5 of 14
[+] Feedback
CY62256VN
Figure 2. Data Retention Waveform
DATA RETENTION MODE VCC 1.8 V tCDR CE VDR > 1.4 V 1.8 V tR
Switching Characteristics
Over the Operating Range[9] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[12, 13]
Description
CY62256VN-70 Min 70 - 10 - - 5 - 10 - 0 - 70 60 60 0 0 50 30 0 - 10 Max - 70 - 70 35 - 25 - 25 - 70 - - - - - - - - 25 -
Unit
Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to low CE LOW to low Z[10] Z[10, 11] Z[10] OE HIGH to high
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE HIGH to high Z[10, 11] CE LOW to power up CE HIGH to power down Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE LOW to high Z[10, 11] WE HIGH to low Z[10]
Notes 9. Test conditions assume signal transition time of 5 ns or less timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOL/IOH and 100-pF load capacitance. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 12. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-06512 Rev. *D
Page 6 of 14
[+] Feedback
CY62256VN
Switching Waveforms
Figure 3. Read Cycle No. 1[14, 15]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 4. Read Cycle No. 2[15, 16]
t RC
CE tACE OE tDOE t LZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT t PU 50%
t HZOE tHZCE DATA VALID t PD
HIGH IMPEDANCE
DATA OUT
ICC 50% ISB
Figure 5. Write Cycle No. 1 (WE Controlled)[17, 18, 19]
tWC ADDRESS
CE tAW WE tSA t PWE tHA
OE tSD DATA I/O NOTE 20 t HZOE
Notes 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW. 17. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 18. Data I/O is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 20. During this period, the I/Os are in output state and input signals should not be applied.
tHD
DATAINVALID
Document Number: 001-06512 Rev. *D
Page 7 of 14
[+] Feedback
CY62256VN
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (CE Controlled)[21, 22, 23]
tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAINVALID t HD tHA tSCE
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)[23, 24]
tWC ADDRESS
CE tAW tSA WE tSD DATA I/O NOTE 25 t HZWE DATA INVALID tLZWE t HD t HA
Notes 21. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 22. Data I/O is high impedance if OE = VIH. 23. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 24. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 25. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 001-06512 Rev. *D
Page 8 of 14
[+] Feedback
CY62256VN
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.8 1.6 1.4 NORMALIZED ICC 1.2 1.0 0.8 0.6 0.4 0.2 2.4 2.8 1.6 1.8 2.0 3.2 3.6 TA= 25C 1.4 1.2 1.0 ISB2 A 0.8 0.6 0.4 0.2 0.0 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 2.5 NORMALIZED tAA 2.0 1.6
VCC = 3.0V
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE
VCC = 3.0V
STANDBY CURRENT vs. AMBIENT TEMPERATURE 3.0 2.5 2.0
3. 3V
NORMALIZED ICC
1.5 1.0 0.5 0.0 ISB
V
cc
55
25
125
-0.5
55
25
=
105
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT 14 vs. OUTPUT VOLTAGE 12 10 8 6 4 2 0 0.0 1.0 2.0 3.0
TA = 25C
NORMALIZED tAA
1.4 1.2 1.0 0.8 0.6
1.5 1.0 0.5 0.0 1.65 TA = 25C
2.1
2.6
3.1
3.6
55
25
125
OUTPUT SINK CURRENT (mA)
SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT (mA)
AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE -14 -12 -10 -8 -6
TA = 25C
OUTPUT VOLTAGE (V)
-4 0 0.0 0.5 1.0 1.5 2 2.5
OUTPUT VOLTAGE (V)
Document Number: 001-06512 Rev. *D
Page 9 of 14
[+] Feedback
CY62256VN
Typical DC and AC Characteristics
(continued)
NORMALIZED ICC vs. CYCLE TIME 1.25 NORMALIZED ICC
VCC = 3.0V
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 DELTA tAA (ns) 25.0 T = 25C A VCC = 3V 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000
1.00 TA = 25C VIN = 0.5V
0.75
0.50 1
10
20
30
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect, output disabled Mode Deselect/power down Active (ICC) Active (ICC) Active (ICC) Power Standby (ISB)
Document Number: 001-06512 Rev. *D
Page 10 of 14
[+] Feedback
CY62256VN
Ordering Information
Speed (ns) 70 Ordering Code CY62256VNLL-70ZXC CY62256VNLL-70SNXI CY62256VNLL-70ZXI CY62256VNLL-70ZRXI CY62256VNLL-70SNXE CY62256VNLL-70ZXE Package Diagram 51-85071 51-85092 51-85071 51-85074 51-85092 51-85071 Package Type 28-pin TSOP I (Pb-free) 28-pin (300-mil) Narrow SOIC (Pb-free) 28-pin TSOP I (Pb-free) 28-pin Reverse TSOP I (Pb-free) 28-pin (300-mil) Narrow SOIC (Pb-free) 28-pin TSOP I (Pb-free) Automotive-E Operating Range Commercial Industrial
Contact your local Cypress sales representative for availability of other parts
Ordering Code Definitions
CY 62 256 V N LL - 70 XXX X
Temperature Grade: X = C or I or E C = Commercial = 0 C to +70 C; I = Industrial = -40 C to +85 C; E = Automotive-E = -40 C to +125 C Package Type: XXX = ZX or SNX or ZRX ZX = 28-pin TSOP I (Pb-free) SNX = 28-pin Narrow SOIC (Pb-free) ZRX = 28-pin Reverse TSOP I (Pb-free) Speed Grade Low Power Nitride Seal Mask fix Voltage Range (3 V Typical) Density: 256 Kbit MoBL SRAM family Company ID: CY = Cypress
Document Number: 001-06512 Rev. *D
Page 11 of 14
[+] Feedback
CY62256VN
Package Diagrams
Figure 8. 28-pin (300-mil) SNC (Narrow Body), 51-85092
51-85092 *C
Figure 9. 28-pin TSOP 1 (8 x 13.4 mm), 51-85071
51-85071 *H
Document Number: 001-06512 Rev. *D
Page 12 of 14
[+] Feedback
CY62256VN
Figure 10. 28-pin Reverse TSOP 1 (8 x 13.4 mm), 51-85074
51-85074-*F
Document Number: 001-06512 Rev. *D
Page 13 of 14
[+] Feedback
CY62256VN
Document History Page
Document Title: CY62256VN 256K (32K x 8) Static RAM Document Number: 001-06512 Rev. ** *A *B *C *D ECN No. 426504 488954 2769239 2901521 3119519 Submission Date See ECN See ECN 09/25/09 03/30/2010 01/04/2011 Orig. of Change NXR NXR New Data Sheet Added Automotive product Updated ordering Information table Removed inactive parts from Ordering Information. Updated Package Diagram Updated Ordering Information. Added Ordering Code Definitions. Description of Change
VKN/AESA Corrected VIL description in the Electrical Characteristics table AJU AJU
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06512 Rev. *D
Revised January 4, 2011
Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

▲Up To Search▲

Price & Availability of CY62256VNLL-70ZRXI

	To Download CY62256VNLL-70ZRXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .